This invention relates to a semiconductor device and, more particularly, to a differential negative resistance element and a process for fabricating the differential negative resistance element.
It has been proposed to modulate the base resistance of a bipolar transistor with the collector voltage. The bipolar transistor exhibits the collector current-to-collector voltage characteristics on the basis of the differential negative resistance. Such a differential negative resistance device and a process for fabricating the device are disclosed by Y. H. Wang et al. in xe2x80x9cDemonstration of high Peak-to- Valley Current Ratio in an N-P-N AlGaAs/GaAs Structurexe2x80x9d, J. Appl. Phys., vol. 73, pages 7990.
The structure of the prior art differential negative resistance device is shown in FIG. 1. The prior art differential negative resistance device comprises a substrate 1, a collector layer 2 of one conductivity type, a base layer 3 of the opposite conductivity type and an emitter layer 4 of the one conductivity type. The substrate 1 is formed of heavily-doped n-type GaAs. The collector layer 2 is formed of lightly doped n-type GaAs, which is grown on the upper surface of the substrate 1. The base layer 3 is formed of heavily doped p-type GaAs, which is grown on a predetermined area of the upper surface of the collector layer 2. The emitter layer 4 is formed of n-type Alxe2x80x94GaAs, which is grown on the upper surface of the base layer 3.
The prior art differential negative resistance element further comprises a collector electrode 5, a base electrode 6, an emitter electrode 7 and a heavily doped p-type region 12. The collector electrode 5 is formed of AuGe/Au alloy, and is held in contact with the lower surface of the substrate 1. The heavily doped p-type region 12 is formed in a surface portion of the collector layer 2, and laterally extends to the predetermined area of the collector layer 2 under the base layer 3. The base electrode 6 is formed of AuZn/Au alloy, and is held in contact with the heavily doped p-type region 12. The emitter electrode 7 is formed of AuGe/Au alloy, and is held in contact with the upper surface of the emitter layer 4.
The emitter electrode is connected to the ground, and a positive constant voltage is applied to the base electrode 6. The collector electrode 5 is swept from zero volt to a certain positive voltage. The surface portion of the collector layer 2 is inverted to the p-type, and the inverted layer serves as a p-type channel for the holes. While the collector voltage is varied in a relatively small voltage range, the base electrode 6 is electrically connected to the base layer 3 through the p-type channel region, and the base current flows between the base electrode 6 and the base layer 3. The base current gives rise to the bipolar transistor action, and the collector current flows.
The collector voltage is increased. The p-type channel in the surface portion of the collector layer 2 is reduced, and the p-type channel is increased in resistance. Accordingly, the base current is reduced, and the collector current is reduced together with the base current. This results in the differential negative resistance.
The collector voltage is further increased. The p-type channel is perfectly eliminated from the surface portion of the collector layer 2, and the base electrode 6 is changed to the open-state. As a result, the collector current does not flow. The peak current and the valley current under the differential negative resistance are corresponding to the on-current and the off-current in a standard bipolar transistor, and the ratio between the peak current and the valley current, i.e., the on/off ratio is much larger than that of the standard bipolar transistor.
Description is hereinbelow made on the process for fabricating the prior art differential negative resistance element. First, the substrate 1 of heavily doped n-type GaAs is prepared. The substrate 1 is placed in a reaction chamber of a molecular beam epitaxial growing system, and the lightly doped n-type GaAs, the heavily doped p-type GaAs and the n-type Al0.3Ga0.7As are successively grown on the heavily doped n-type GaAs substrate 1. The lightly doped n-type GaAs is doped with silicon of the order of 5xc3x971016 cmxe2x88x923, and is grown to 500 nanometers thick for the collector layer 2. The heavily doped p-type GaAs is doped with beryllium of the order of 5xc3x971018 cmxe2x88x923, and is grown to 200 nanometers thick for the base layer 3. The n-type Al0.3Ga0.7As is doped with silicon of the order of 5xc3x971017 cmxe2x88x923, and serves as the emitter layer 4.
Subsequently, the n-type Al0.3Ga0.7As layer and the heavily doped p-type GaAs layer are partially etched away so as to leave the base layer 3 and the emitter layer 4 on and over the predetermined area of the upper surface of the collector layer 2. When the etching is completed, the other area of the upper surface of the collector layer 2 is exposed. Au-Zn alloy is evaporated onto the exposed surface of the collector layer 2, and the base electrode 6 is formed on the exposed surface of the collector layer 2. Thereafter, the resultant structure is treated with heat at 450 degrees in centigrade. While the resultant structure is being treated with heat, Zn is diffused from the base electrode 6 into the surface portion of the collector layer 2, and forms the heavily doped p-type region 12 in the collector layer 2. The diffused Zn serves as the acceptor, and makes the surface portion of the collector layer 2 serve as the p-type channel. Finally, AuGe/Au is evaporated onto the lower surface of the substrate 1 and the upper surface of the emitter layer 4, and forms the collector electrode 5 and the emitter electrode 7 on the lower surface of the substrate 1 and the upper surface of the emitter layer 4, respectively.
As described hereinbefore, the p-type channel between the base electrode 6 and the base layer 3 is controlled with the collector voltage, and needs satisfying the following two requirements, which are contrary to each other. The first requirement is that the p-type channel extends from the region under the base electrode 6 to the region under the base layer 3. The second requirement is that the p-type channel is thin enough to control. However, it is difficult to satisfy both of the first and second requirements concurrently.
The p-type channel is formed by Zn, which was diffused from the base electrode 6, and the base electrode 6 is laterally spaced from the base layer 3. If the heat treatment is continued for a long time, Zn can reach the region under the base layer 3. However, Zn is also diffused in the direction of depth during the heat treatment, and makes the p-type channel thick. The thick p-type channel is hardly controlled with the collector voltage. On the other hand, if the heat treatment is shortened, the p-type channel is made to be thin. However, Zn does not reach the region under the base layer 3. In the circumstances, it is necessary for the manufacturer to locate the base electrode 6 at the optimum position on the collector layer 2, and the diffusion is strictly controlled for satisfying the two requirements. For this reason, the p-type channel is not reproducible. This is the first problem inherent in the prior art differential negative resistance element.
Another problem is a relatively small ratio between the peak current and the valley current. This is because of the fact that the boundary between the collector layer 2 and the p-type channel is gentle, i.e., not sharp. The collector voltage can not sharply modulate the channel resistance, and the ratio is relatively small.
It is therefore an important object of the present invention to provide a differential negative resistance element, which achieves a large ratio between the peak current and the valley current.
It is also an important object of the present invention to provide a process, through which a base electrode is electrically connectable to a base layer through a thin channel to be promptly controlled with a collector voltage.
To accomplish the object, the present invention proposes to use a base layer as a channel layer. The base layer is made to be thin enough to vary the base resistance with a collector voltage. The thickness of the base layer is easily controllable, and the channel in the thin base region is well reproducible. The channel resistance is dominated by the thickness of the base region and the dopant concentration therein. The present inventor found the optimum range of the product between the thickness and the dopant concentration to be from 1xc3x971011 cmxe2x88x922 to 1xc3x971013 cmxe2x88x922. When the product is fallen within this range, the channel sharply varies the resistance depending upon the collector voltage.
In accordance with one aspect of the present invention, there is provided a differential negative resistance element comprising a multi-layered semiconductor structure formed on a substrate and including a first semiconductor layer having a first conductivity type and serving as one of a collector region and an emitter region of a bipolar transistor, a second semiconductor layer having a second conductivity type opposite to the first conductivity type and serving as a base contact region, a base region and a channel region located between the base contact region and the base region and a third semiconductor layer having the first conductivity type and serving as the other of the collector region and the emitter region, and collector, base and emitter electrodes serving as ohmic electrodes respectively connected to the collector, the base contact region and the emitter region, wherein the channel region is reduced in thickness so as to vary an electric resistance with a collector voltage applied to the collector electrode. In accordance with another aspect of the present invention, there is provided a process for fabricating a differential negative resistance element comprising the steps of a) successively growing a first semiconductor layer having a first conductivity type and serving as one of a collector region and an emitter region of a bipolar transistor, a second semiconductor layer having a second conductivity type opposite to the first conductivity type and serving as a base contact region, a base region and a channel region located between the base contact region and the base region and a third semiconductor layer having the first conductivity type and serving as the other of the collector region and the emitter region on a substrate, b) partially etching the third semiconductor layer so as to expose a portion of the second semiconductor layer, c) partially etching the portion of the second semiconductor layer so as to form the channel region between the base contact region and the base region so that a collector voltage applied to the collector electrode varies an electric resistance in the channel region and d) forming a collector electrode, a base electrode and an emitter electrode held in contact with the collector region, the base contact region and the emitter region in an ohmic manner.